The availability of high speed integrated circuit chips has resulted in a need for suitable interconnection technology that offers high wiring density, good electrical characteristics for the propagation of high speed signals, and good thermal performance. Multilayer interconnection systems with fine line conductors and associated ground planes have been proposed for applications in high performance systems. C. W. Ho et al., IBM J. Res. Dev., 26:286-296 (May 1982), and C. W. Ho et al., VLSI Electronics: Microstructure Science, 5(3):103-143 (Academic, New York, 1982). Fine geometry copper conductor lines defined in a photolithographically patterned layer of a low-dielectric constant polymer, such as a polyimide, have emerged as a versatile packaging approach for the conductive interconnection lines between densely packed integrated circuit chips in high performance systems.
One prior approach to fabricating interconnect structures uses copper conductor lines that are several microns thick. The metal is deposited using a thin film technique and is subsequently patterned using a resist mask. A wafer substrate with the patterned conductor lines is then spin-coated with a dielectric (e.g., polyimide). Planarity of the overall layer, which is of crucial importance for good performance and manufacturing yield, is poor unless one employs multiple coats of the dielectric film. The process is tedious and due to the presence of thick dielectric films, the interconnect structures are subjected to high levels of stress, resulting in poor yields and lowered reliability.
An alternative approach, which circumvents the limitations of the approach described above, uses photosensitive polyimide as the dielectric. In this approach, the polyimide film is photopatterned to create trenches into which the copper conductor lines are electroplated to a height equal to the polyimide film thickness, thus assuring near perfect planarity of all the individual signal layers. See K. K. Chakravorty, Proc. of Elect. Comp. Conf., 135-142 (1988); and Chakravorty et al., Proc. 3rd Int. SAMPLE Elec. Conf., 3:1213-1223 (1988).
In general, the alternative approach utilizes the following steps to produce conductive features having fine geometry: (1) depositing a thin layer of a base metal layer (also referred to as a metallic seed layer) on a dielectric substrate, (2) patterning the base metal layer to form fine geometry lines that serve as the electroplating base for the conductor lines, (3) spin-coating a layer of a photosensitive dielectric (e.g., photosensitive polyimide) over the dielectric substrate and patterned base metal layer, (4) photolithographically patterning the layer of the photosensitive dielectric to form dielectric features (defined by trenches) having fine geometry, and also uncovering the base metal layer at the bases of the features, and (5) electroplating an electrically conductive material between the patterned dielectric features onto the base metal layer to form electrically conductive features.
The alternative approach requires the presence of an electroplating base metal layer in the polyimide trenches, which needs to be electrically connected to the cathode of the electroplating bath during step (5), described above. A typical multichip module substrate may use a design such that it is not possible to extend every interconnection line to the edge of the module so as to electrically connect it to the cathode of the electroplating bath. In order to make this alternative approach work under such conditions, a technique is required whereby the "isolated" lines may be electrically connected to the edge and, thus, the cathode of the bath during the electroplating step. Upon completion of the plating process, the electrical connection may then be severed, restoring the electrical isolation of the conductor lines. This approach can be used for each layer in a multlayer high-density interconnect structure.
There are a few known ways of forming these temporary electrical connections to the outer edge of the substrate so that electroplating of "isolated" lines can be carried out. One such method is disclosed in U.S. Pat. No. 4,661,214 (Young). The Young patent proposes a type of microfuse that remains electrically conductive during normal processing temperatures but upon heating to a higher temperature, the material forming the fuse is transformed into an electrically insulating state. The Young patent proposes a silver/silver halide or silver/chalcogenide system as a thin film microfuse. The activation mechanism to electrically disconnect the thin film silver/silver halide microfuse is based on thermal interdiffusion between the silver and silver halide, which causes the insulating silver halide layer to absorb the metal film, thereby breaking the electrical connection. However, this interdiffusion mechanism imposes several limitations which influence its performance:
Control of the stoichiometric composition of the silver halide or chalcogenide film is difficult. Such control is important because the stoichiometry affects the temperature of disconnection. PA1 Step coverage is a problem. Only thin films of silver can be used; otherwise, the structure may not disconnect. The disconnection of thicker layers is very difficult because it is controlled by the silver gradient and the diffusion coefficient. PA1 The thickness of each component must be stringently controlled to ensure completion of thermal intermixing and hence, disconnection, at the proper temperature. PA1 Chlorine based by-products generated in final heating or irradiation may cause corrosion. PA1 Finally, the silver film adheres poorly.
Another approach to fabricating high-density multilayer interconnect structures involving interconnection of structures during the electroplating process followed by their isolation, was disclosed by Chakravorty and Tanielian in U.S. Ser. No. 520,174, filed on May 7, 1990. In this method, a blanket tantalum layer is used to electrically connect all of the electroplating seed layers to the edge of the wafer. Also, a dense anodic tantalum oxide layer is grown on the top of the tantalum layer. Upon completion of an electroplating process, excess tantalum/tantalum oxide layer is etched off to render the lines electrically isolated once again.
In spite of the above methods, there has remained a need for new and improved methods of temporarily electrically connecting conductors, such as plating seed layers to enable electroplating of conductor lines. In particular, there is a need for a new type of microfuse that does not suffer from the deficiencies of the Young patent.
It is therefore an object of the present invention to provide a new disconnect system to overcome limitations in prior approaches and/or to provide an alternative to prior methods.
It is also an object of the present invention to provide new methods for electrically isolating conductive features on a substrate.
It is yet another object of the present invention to provide methods of fabricating layers of multilayer high-density interconnect structures.
It is yet another object of the present invention to provide interconnect structures and multichip modules by way of an electroplating method that does not suffer from the drawbacks of prior approaches involving temporary electrical connections.
The above and other objects as will hereinafter become more readily apparent, have been achieved by the present invention, which is based on the discovery that a zinc layer can be utilized to temporarily electrically connect conductors. In a preferred embodiment, a zinc conductor layer is utilized in accordance with the present invention to temporarily connect seed layers on a substrate to enable electroplating of conductive features to be carried out, followed by electrically isolating the conductive features by converting the zinc layer into an insulating state. Conversion of the zinc layer to the insulating state may be accomplished by heating or by irradiation with energy in the form of a laser beam, and the like. Because of the function of the zinc layer and the typical small dimensions of interconnect structures, the zinc layer herein acts as a microfuse.
In a preferred embodiment of the present invention, the microfuse includes an adhesion layer, which enhances adherence of the zinc layer to the substrate and the base metal layer, and a protection layer coating the zinc layer, which protects the conductor layer from side reactions that diminish conductivity of the zinc layer prior to the desired conversion to an insulating state. When heating is used to convert the zinc layer to an insulating layer, the zinc layer is intended to be conducting, and therefore usable in an electroplating process, until it is heated to about 400.degree. C. for at least about one hour. Preferably, the adhesion and protection layers both comprise silicon; therefore, a microfuse made up of all three layers may be referred to as a Si/Zn/Si microfuse.
As noted above, the inventive methods involve electrical disconnection by converting a conductive zinc layer into an insulating layer comprising zinc oxide. Zinc oxide has a very high glass transition temperature so it is thermodynamically very stable. This leads to long term reliability for the overall interconnect system.
Other objects, features, applications, and advantages of the present invention will be readily apparent from the following description of certain preferred embodiments thereof, taken in conjunction with the accompanying drawings. It is to be understood that variations and modifications may be effected without departing from the spirit and scope of the novel concepts of the disclosure herein.